The present invention relates to a phase locked loop, and more particularly, to a phase locked loop with a cycle slip detector.
Phase Locked Loops (PLLs) are used in many types of communication systems. Recently, the advances in modern technology have greatly extended their scope, and they can now also be found in many systems ranging from data recovery circuits to frequency synthesizers.
A conventional analog PLL is a closed loop feedback circuit whose function is to produce a clock signal synchronized in phase and frequency with an external reference signal. It achieves this by controlling the phase of the generated clock signal so that the phase error between the clock signal and the reference signal is kept at a minimum. In the digital domain, a digital PLL having digital circuitry is applied nowadays.
Please refer to FIG. 1, which is a diagram of a related art digital phase locked loop (PLL) 10. The PLL 10 includes a phase detector (PD) 12 with two inputs Si, So, for determining the phase difference between these inputs Si, So and generating an error signal Se indicating this phase difference; a loop filter 14 for low pass filtering of the error signal Se and producing a control signal Sc corresponding to the error signal Se; and a digitally-controlled oscillator (DCO) 16 for generating the signal So in response to the control signal Sc outputted from the loop filter 14. As shown in FIG. 1, the signal So having a specific frequency controlled by the control signal Sc is further fed back to the phase detector 12. The phase detector 12 continuously detects the phase error according to the signals Si and So, and the loop filter 14 continuously updates the control signal Sc on reception of the error signal Se. Therefore, the DCO 16 (for example, a numerically-controlled oscillator) keeps updating the frequency of the signal So to reduce the phase error between the signals Si and So. In this manner, the DCO 16 is driven by the control signal Sc to vary its output frequency in a frequency sweeping direction that ideally reduces the phase error, hence the PLL 10 replicates and tracks the frequency and phase at the PLL input. When this occurs, the PLL 10 is in lock.
It is well known that the PLL 10 can lock the signal So to a desired phase if the phase difference between the signals Si and So is not greater than 2π. If, however, the phase difference between the signals Si and So is greater than 2π (i.e. a cycle slip occurs), the phase detector 12 is now presented with a large discrepancy in phase, causing the DCO 16 to carry out frequency sweeping in a direction away from the target frequency, and causing the PLL 10 to lock the signal So to an erroneous phase. A significant amount of time is required to lock on to the correct phase once more.